The design of integrated circuits typically includes several phases. Before mass production of the integrated circuits, prototypes are typically made to verify the design of the integrated circuits. Field programmable gate array (FPGA) and cell based design (CBD) are among the most commonly used design methods.
FIG. 1 illustrates a FPGA design, which includes a plurality logic units placed in an array, with predefined interconnects (not shown) built in. The FPGA may be programmed through an anti-fuse switch box (not shown), so that chips having a same FPGA design may be used to implement different circuits having different functions. Additional functional modules, such as embedded memories and processors, may be built in the FPGA chips. Since one FPGA design may be shared by multiple applications, the design cost is also shared by the multiple applications, and hence is relatively low. Further, the design cycle is short due to the fact that existing FPGA design may be used without the need to start from scratch. However, limited by the low performance of the resulting circuits, FPGA is only suitable for low-volume production with high unit cost, and is often used only in prototype design.
CBD methodology, on the other hand, is generally used for application specific integrated circuit (ASIC) design, as shown in FIG. 2. CBD design may adopt standard cells to implement the integrated circuits and the standard cells are typically arranged into rows. However, the placement of the standard cells is customized from application to application, and a row may include different standard cells. The logic functions are implemented through interconnected standard cells. Accordingly, the interconnection, as a result of the randomly placed standard cells, is also not fixed. Custom macros, such as embedded memories and analog macros, can be included in the CBD and randomly placed within the respective chips. Due to the customized design, the circuits designed adopting the CBD methodology typically enjoy high performance.
The CBD methodology also suffers from drawbacks. When the integrated circuits are formed using 45 nm technology and below, all CBD design based on conventional design rules starts to suffer from serious process variations, which may be as great as about 30 percent. This causes significant reduction in the performance yield. On the other hand, since all of the base layer (the layer including active regions and gate electrodes) and metal layers are customized, the cost of the design using the CBD methodology is also high. For example, the design may cost about half a million dollars or more. The cycle time is also long, with typically more than 12 weeks required if advanced nano-technologies are to be adopted.
Accordingly, what is needed in the art is a design methodology that may combine the advantageous features of the flexibility and low cost of FPGA, and the high performance of CBD.